Configuration register 0 for unit 1
| FILTER_THRES_U | This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. |
| FILTER_EN_U | This is the enable bit for unit %s’s input filter. |
| THR_ZERO_EN_U | This is the enable bit for unit %s’s zero comparator. |
| THR_H_LIM_EN_U | This is the enable bit for unit %s’s thr_h_lim comparator. Configures it to enable the high limit interrupt. |
| THR_L_LIM_EN_U | This is the enable bit for unit %s’s thr_l_lim comparator. Configures it to enable the low limit interrupt. |
| THR_THRES0_EN_U | This is the enable bit for unit %s’s thres0 comparator. |
| THR_THRES1_EN_U | This is the enable bit for unit %s’s thres1 comparator. |
| CH0_NEG_MODE_U | This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter |
| CH0_POS_MODE_U | This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter |
| CH0_HCTRL_MODE_U | This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification |
| CH0_LCTRL_MODE_U | This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification |
| CH1_NEG_MODE_U | This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter |
| CH1_POS_MODE_U | This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter |
| CH1_HCTRL_MODE_U | This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification |
| CH1_LCTRL_MODE_U | This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification |